LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_textio.all;
use std.textio.all; 

entity file_in is
end file_in;

architecture get_input of file_in is
-- signal clock,eof : bit := '0';                               --period of clock,bit for indicating end of file.

 signal data_in : std_logic_vector(499 downto 0);               --data read from the file.
 
  begin
  
  -- clock <= not (clock) after 1 ns;                             --clock with time period 2 ns

  reading :
  process
      file in_file : text open read_mode is "/home/ecegrid/a/mg114/ece337/puece337-hdacontroller/test_io/tb_input.txt";     --declare input file
      variable in_line : line;                                  --declare line number
      variable data_read : std_logic_vector(499 downto 0);      --data read from the file.
      variable c1 : std_logic;                                  --temporary place for data after its read
    
  begin
  --  wait until clock = '1' and clock'event;
    while not endfile(in_file) loop                             --checking if the "END OF FILE" is reached
      readline(in_file, in_line);                               --reads a line from the file
      read(in_line, c1);                                        --reads bit on the line
      data_read := data_read(498 downto 0) & c1;                --shifts desired bit into input variable
--      wait for 10 ns;
    end loop;
  
    data_in <= data_read;                                       --puts the value available in variable into a signal
    wait;                         
  end process reading;

end get_input;
